Similar Jobs

20 jobs similar to Senior RTL Design Engineer (Wireless SoC / Modem) at SYMPHISYS SOFTWARE CONSULTING

SoC Verification Engineer (UVM / Low Power / IP Verification)

SYMPHISYS SOFTWARE CONSULTING

11–15 yrsHyderabad

11–15 yrsHyderabad

yesterday

R

Senior PCIe CXL RTL Design Engineer

Rambus Inc.

7–10 yrsBengaluru

7–10 yrsBengaluru

22 hours ago

Sr/Staff AE For Physical Implementation RTL-GDS

Synopsys

5–10 yrsBengaluru

5–10 yrsBengaluru

last week

Analog Design Engineer (EDA Tools / Cadence Virtuoso)

SYMPHISYS SOFTWARE CONSULTING

11–15 yrsHyderabad

11–15 yrsHyderabad

yesterday

Emulation Engineer

SYMPHISYS SOFTWARE CONSULTING

8–13 yrsHyderabad

8–13 yrsHyderabad

yesterday

S

RTL Design Sr Engineer & Lead

SCIHUBSS

2–10 yrsHyderabad

2–10 yrsHyderabad

22 hours ago

A

Power Domain Verification Lead

Axiado

10–15 yrsHyderabad

10–15 yrsHyderabad

yesterday

Principal Engineer - FPGA/ASIC, RTL Design - [ID 017]

Vitestork Consulting Private Limited

10–15 yrsHyderabad

10–15 yrsHyderabad

2 days ago

Software Engineering Manager Embedded Wireless Networking

Silicon Labs

10–15 yrsHyderabad

10–15 yrsHyderabad

6 days ago

A

Senior Staff ASIC Design Engineer

Axiado

12–17 yrsHyderabad

12–17 yrsHyderabad

yesterday

ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN

Cisco Systems

12–17 yrsHyderabad

12–17 yrsHyderabad

yesterday

A

Lead Design Verification Engineer

Altera

8–13 yrsHyderabad

8–13 yrsHyderabad

yesterday

Lead AMS Verification Engineer IP

Vitestork Consulting Private Limited

8–12 yrsHyderabad

8–12 yrsHyderabad

yesterday

ASIC Design Verification Lead

Einfochips

8–13 yrs800k - 1.5MHyderabad

8–13 yrsHyderabad

800k - 1.5M

yesterday

A

Senior ASIC Verification Engineer

Axiado

8–13 yrsHyderabad

8–13 yrsHyderabad

yesterday

Senior Staff Simulation Engineer

TekWissen

8–12 yrsHyderabad

8–12 yrsHyderabad

4 days ago

STA Engineer - Staff / Sr. Staff

Vitestork Consulting Private Limited

8–15 yrsHyderabad

8–15 yrsHyderabad

6 days ago

L

Sr. Staff RTL Eng

LATTICE SEMICONDUCTOR (INDIA) PRIVATE LIMITED

14–19 yrsPune

14–19 yrsPune

22 hours ago

L

AMS Verification Image Editor (DV oriented)

Leadic Design

7–9 yrsHyderabad

7–9 yrsHyderabad

2 days ago

Principal IO Mixed Signal Design Engineer

Microchip Technology

7–12 yrsHyderabad

7–12 yrsHyderabad

4 days ago