Experience
10 - 15 yrs
Job Location
Hyderabad, India
Vacancy
1
Designation
Principal Asic Design Engineer
Job Type
Not specified
Job Description
1) Principal Engineer - FPGA/ASIC, RTL Design - [ID 017]
Job Description
- Responsibilities:
Excellent Leading communication skills and demonstrate the desire to take on diverse challenges.
Experienced with large FPGA development flow and tools on Xilinx devices.
Experience in wireless communication
Proficient in Verilog RTL language. Experienced with large FPGA development on Xilinx devices.
Very familiar with Xilinxs build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure.
Hands on with lab FPGA debug methodologies.
Hands on experience with lab debug equipment, such as oscilloscopes and logic analysers.
Experience with verification methodologies, RTL and gate level simulations and debug.
Experience debugging silicon and PCB issues.
Run basic verification tests (on simulations)
Minimum Qualifications:
BSc/ MSc in Electr
Skills:
FPGA Design, RTL, ASIC Design
Job Location:
Hyderabad
Experience:
10+ Years
Company Name:
Startup RD - Telecommunication Semiconductors
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