Experience
8 - 13 yrs
Job Location
Hyderabad, India
Vacancy
1
Designation
Lead Verification Engineer
Job Type
ONSITE
Job Description
Performs functional logic verification of an FPGA to ensure design will meet specification requirements
Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications
Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs
Replicates, root causes, and debugs issues in the pre-silicon environment
Finds and implements corrective measures to resolve failing tests
Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features
May also collaborate with systems and software engineers to support integration testing of the FPGA
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams
Maintains and improves existing functional verification infrastructure and methodology
Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (eg, gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications
Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications
Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs
Replicates, root causes, and debugs issues in the pre-silicon environment
Finds and implements corrective measures to resolve failing tests
Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features
May also collaborate with systems and software engineers to support integration testing of the FPGA
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams
Maintains and improves existing functional verification infrastructure and methodology
Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (eg, gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications
Minimum Qualification:
Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience
Related technical experience should be in/with: Pre Silicon Validation/Verification
OVM/UVM, System Verilog, constrained random verification methodologies
Related technical experience should be in/with: Pre Silicon Validation/Verification
OVM/UVM, System Verilog, constrained random verification methodologies
Preferred Qualification:
Design Verification with developing, maintaining, and executing complex IPs and/or SOCs
The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure)
Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies
Experience in FPGA architecture or FPGA prototyping
The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure)
Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies
Experience in FPGA architecture or FPGA prototyping