Experience
8 - 12 yrs
Job Location
Hyderabad, India
Vacancy
1
Designation
Lead Verification Engineer
Job Type
ONSITE
Job Description
1) Lead AMS Verification Engineer - IP, SOC - [ID 014]
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying. Job Description
- Lead the planning, development, and execution of AMS verification strategies for analog/mixed-signal IPs and SoCs.
Define and implement verification plans, including testbenches, stimulus generation, and checking strategies.
Develop and maintain SystemVerilog, Verilog-AMS, or UVM-based verification environments.
Perform co-simulation of analog/digital designs using industry tools (e.g., Cadence, Synopsys, Siemens EDA).
Conduct mixed-signal simulations, behavioral modeling of analog blocks, and integration into top-level environments.
Collaborate with analog designers to create AMS behavioral models (e.g., Verilog-A/AMS) for early integration and verification.
Debug complex AMS simulation issues across multiple abstraction levels.
Drive coverage analysis and sign-off using functional, formal, and assertion-based methods.
Mentor and guide junior engineers in best practices, methodologies, and
Skills:
SV , UVM , Mixed Signal Verification
Job Location:
Bangalore, Hyderabad, Ahmedabad, Noida
Experience:
8 - 12 Years