Staff Engineer, Digital Design Engineering

• RTL front-end design. Design of IP and full chip integration including architecture, microarchitecture, logic design, LINT, Clock Domain Crossing Analysis.
• Own major blocks in a design and provide technical guidance to the team.
• Work with the DV team to ensure proper closure of the owned blocks in terms of functionality, code coverage etc
• Interface with applications and test for any silicon debug by providing the necessary data for analysis and for resolving issues.
• Own some front-end implementation flows for an IC.
• Develop Design and Implementation to enable best possible PPA, robust product quality and design for debug and test.
• Use of AI tools as needed for productivity or methodology improvements

• Solid understanding of digital design concepts, micro architecture.
• Hands on experience on front end implementation tools for Lint, CDC. Knowledge of concepts for Equivalence Check, Synthesis & STA, Power estimation tools.
• Hands on experience on IP level verification or unit testing
• Good understanding of the entire ASIC design flow involving logic design, verification, synthesis, timing and backend.
• Understanding of ASIC synthesis, constraints development & analysis, STA, & DFT.
• Hands on experience or good understanding of gate level simulations
• Must be able to work autonomously and guide others based on changing priorities.
• Ability to learn, adapt & improve on to new methodologies and technologies.
• Experience in high speed design and communications such as I2C, UART, SPI.
• Excellent analytical and debugging skills and the ability to proactively solve issues.
• Must be a highly motivated with good aptitude and attitude.
• Good cross functional collaboration, communication & interpersonal skills.
• Knowledge of protocols such as HDMI, DP, MIPI, ethernet protocols an added advantage.
• Knowledge of functional safety design an added advantage.

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