Staff Engineer, Digital Design Engineering

• Ownership of developing the specification, micro architecture, and RTL design of modules as per requirements.
• Contribute/influence Chip Architecture.
• Provide Technical and managerial Leadership to Digital Design Engineers in the Design of IPs and functional blocks.
• Guide Junior design engineers working on the development of timing constraints, lint checks, synthesis, and Static-timing-analysis.
• Co-work with the verification and PD team for coverage and timing closure respectively.
• Lint check and Clock domain crossing analysis
• Sanity Synthesis runs.
• Support post silicon debug activities
• Hire , mentor, and guide design engineers technically and managerially.

• Minimum BTech/BE degree in Electrical/Electronics.
• 10+ years of solid digital logic design experience in hands-on and/or technical leadership.
• Strong hands-on RTL coding experience and debugging skills.
• Experience with Lint, CDC, formal equivalence, ECO flows and scripting.
• Knowledge of Audio and/or DSP fundamentals will be an added advantage.
• Good interpersonal, teamwork and communication skills to logically drive the discussions effectively with teams spread geographically.
• Experience in mentoring junior engineers is desirable

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