Experience
8 - 13 yrs
Job Location
Hyderabad, India
Vacancy
1
Designation
Senior RTL Design Engineer
Job Type
Not specified
Job Description
Location : Bangalore
Mandatory Skills :
Spyglass, RDC, CLP, PLDRC, CDC, DC-Compiler,
Strong expertise in Verilog/System Verilog RTL coding and micro-architecture development.
Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable.
Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic.
Experience with wireless modem IPs or similar high-performance digital blocks is a plus.
Familiarity with low-power design methodologies and CDC handling.
Exposure to post-silicon debug and SoC integration challenges.
Design Tool Flows including Spyglass, RDC, CLP, PLDRC, CDC, DC-Compiler, Prime time, synthesis, simulation etc.
Mandatory Skills :
Spyglass, RDC, CLP, PLDRC, CDC, DC-Compiler,
Strong expertise in Verilog/System Verilog RTL coding and micro-architecture development.
Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable.
Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic.
Experience with wireless modem IPs or similar high-performance digital blocks is a plus.
Familiarity with low-power design methodologies and CDC handling.
Exposure to post-silicon debug and SoC integration challenges.
Design Tool Flows including Spyglass, RDC, CLP, PLDRC, CDC, DC-Compiler, Prime time, synthesis, simulation etc.