Physical Verification/RDL Engineer

Physical Verification / RDL Engineer

KEY RESPONSIBILITIES:

• Hands on experience with Block level and Top-level physical verification.
• Good understanding and hands-on experience in lower node technologies. (3nm and below)
• Drive the RDL and MIMCAP closure for complex chiplets
• Collaborate closely with cross-functional teams, including Physical Design, RTL Designers, to facilitate seamless integration and problem resolution.
• Demonstrate strong problem-solving and work well with cross-functional teams
• Good listening, writing, and speaking English
• Good communication skills, strong interpersonal skills and flexibility
• Dedicated, hardworking and good team player
• Familiar with Unix/Linux environment and good at scripts

PREFERRED EXPERIENCE:

• Hands on experience in Physical Verification incl. multi-voltage designs
• Hands on experience in industry standard Place Route tools such as Fusion Compiler, ICC2 and Innovus and also sign off tools like Siemens Caliber etc.
• Strong understanding of low-power flows includes UPF concepts, power-gating, isolation, level-shifter, voltage areas, power-state tables, electrical checks using FM VSI
• Good control over scripting languages like Python, PERL, TCL and strong debug capabilities

ACADEMIC CREDENTIALS:

• Masters or Bachelor s degree in Electronics Engineering
• 8-12 years of experience in Physical Design flow and methodology development on advanced nodes below 3nm
• Proficiency in one or more scripting languages namely Tcl, Perl, sed/awk
• Strong problem-solving skills and analytical thinking
• Team player, good work ethic, and excellent communication skills

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