Experience
6 - 9 yrs
Job Location
Bengaluru, India
Vacancy
1
Designation
Physical Verification Engineer
Job Type
ONSITE
Job Description
Job Title: Physical Verification Engineer - 6-9 Yrs
Location: Bangalore
No. Of positions: 1
Experience required: 6-9 years
The Job Role:
- We are seeking a highly motivated and experienced Physical Verification Engineer to join our VLSI design team.
- The candidate will be responsible for ensuring the physical integrity and manufacturability of complex SoC/IP designs through comprehensive physical verification signoff activities.
- The ideal candidate should have strong expertise in DRC, LVS, ERC, ANTENNA, and advanced-node physical verification flows.
Key Responsibilities:
- Perform physical verification signoff for complex SoC/IP designs at advanced technology nodes (3nm & 2nm etc.).
2. Execute and analyze:
- DRC (Design Rule Check)
- LVS (Layout vs Schematic)
- ERC (Electrical Rule Check)
- Antenna Checks
- Density and DFM checks
3. Debug and resolve physical verification violations by closely working with Physical Design, Layout, and Design teams.
4. Develop and maintain automation scripts for verification flow improvements.
5. Run and analyze signoff tools such as Calibre.
6. Familiarity with Linux and modern software tools and techniques for development
7. Good analytical and problem-solving skills
4. Develop and maintain automation scripts for verification flow improvements.
5. Run and analyze signoff tools such as Calibre.
6. Familiarity with Linux and modern software tools and techniques for development
7. Good analytical and problem-solving skills
Required Qualifications
- Bachelors or Masters degree in Electronics, Electrical Engineering, VLSI, or related field.
- 6-9 years of experience in Physical Verification for SoC/IP development.
- Strong understanding of:
- CMOS fabrication process
- Semiconductor device physics
- Physical Design flow
- Layout methodologies
- Hands-on experience with: Siemens Calibre (DRC/LVS/PERC), Synopsys ICV
- Expertise in advanced technology nodes (3nm and below preferred).
- Experience in debugging complex DRC, LVS, ERC, and antenna violations.
- Proficiency in UNIX/Linux environment.
- Strong scripting skills in Perl, Tcl, Shell, or
Looking for candidates with Full Chip Physical Verification Background
No Referrers Available
There are currently no referrers available for this job. You can still apply, will let you know once there is any referrer available.