FPGA Engineer (DSP/ IP core development)

• Good Experience in VHDL, Verilog based RTL design.
• Must have experience in IP Core Development.
• Experience in using Xilinx ISE, Vivado and Altera Quartus Tool chain.
• Signal Processing Experience, ADC, DDC, FFT, Windowing, Modulation, De-modulation, Filtering, Correlation.
• Should have worked with Peripherals: PCIe, JESD204B, SRIO, Aurora, DDR4, DDR3, Ethernet, AXI4 bus protocol.
• Algorithm Development using MATLAB or similar tools.
• Should have good understanding Timing analysis

Secondary skills:

• Experience in FPGA and Processor integration testing.
• Understanding FPGA requirements and preparing FPGA design/test documents.
• Understanding of DO-254 Standard.