STA/Synthesis/signoff Design and Verification Engineer.

Savvychip Technologies is looking for STA/Synthesis/signoff Design and Verification Engineer. to join our dynamic team and embark on a rewarding career journey

• Perform static timing analysis (STA) to ensure design meets timing requirements.
• Conduct synthesis to translate RTL code into gate-level netlists.
• Optimize designs for power, performance, and area during synthesis.
• Perform signoff verification tasks, including timing, power, and signal integrity analysis.
• Collaborate with cross-functional teams to resolve design and verification issues.
• Document synthesis, STA, and signoff processes and results.