STA (Static Timing Analysis) Engineer

Key Responsibilities

• Perform Static Timing Analysis (STA) for block-level and full-chip ASIC/SoC designs.
• Develop, validate, and maintain SDC timing constraints.
• Analyze and resolve setup, hold, recovery, removal, clock gating, and pulse width violations.
• Perform timing sign-off across multiple PVT (Process, Voltage, Temperature) corners and operating modes.
• Work closely with Physical Design teams to achieve timing closure.
• Debug timing violations and recommend RTL or ECO fixes.
• Perform clock tree analysis and timing optimization.
• Analyze timing reports and provide actionable recommendations.
• Support ECO implementation and timing validation.
• Participate in design reviews and sign-off activities.