Senior/Principal ASIC Design Verification Engineer (SoC/Subsystem)

Role summary
Own end-to-end verification of complex SoCs or large subsystems. This is a hands-on role from testbench architecture to coverage closure, through tapeout and into silicon correlation.

• Architect and build scalable UVM testbenches from scratch at subsystem or SoC level

• Strong hands-on experience in testbench development

• Define verification strategy and author test plans from specs and micro-architecture

• Develop constrained-random and directed tests, scoreboards, checkers, assertions (SVA), and coverage models

• Drive functional, code, and assertion coverage closure with discipline

• Debug complex issues using waveforms, logs, and root-cause analysis

• Lead SoC-level verification: IP integration, coherency, low-power modes, resets/boot, and performance validation

• Work closely with RTL, architecture, DFT, and firmware teams

• Support silicon bring-up and pre-/post-silicon correlation

• 8+ years of hands-on ASIC verification (FPGA/emulation-only experience does not count)

• Strong TB Architecture ownership design, reuse strategy, scalability, and maintainability

• Multiple production ASIC tapeouts with SoC or large subsystem ownership

• Expert in SystemVerilog, UVM, SVA, and constrained-random methodologies

• Deep experience with AXI/ACE, DDR, PCIe, coherency, memory and interrupt fabrics

• Proven strength in test planning, stimulus strategy, checkers/scoreboards, and closure execution

• Excellent debug skills across simulation and silicon correlation