Job Description
Senior Design Verification Engineer
Requirements
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Electronic Engineering/Computer Engineering degree with 5-8 years of progressive experience in digital design and verification.
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Must have demonstrated experience in developing UVM-based testbench infrastructure from ground up, functional cover point development, functional & code coverage analysis/closure and assertion development.
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Experience on both IP and SoC level verification with working knowledge of gate level simulations.
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Knowledge in AHB/AXI/APB protocols is desirable; Experience in Power aware simulations or Formal Verification is a big plus.
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Proficiency in Scripting languages and utilities including Makefile, Python, Perl etc.
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Must be a self-starter, should be able to work on assignments with minimal directions.
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Experience collaborating with product development groups spread across the globe is a must; should have strong interpersonal and communication skills.
Responsibilities
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Verification of key digital blocks in differentiated mixed signal SOCs targeted for the consumer market
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Complete verification ownership Testbench Architecture, Testplan and Testbench Development, Functional Coverage Closure and Code Coverage Closure
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Usage of industry standard methodologies like UVM and constrained random approach to achieve verification goals
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Actively explore and deploy ML techniques to achieve faster turnaround time
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Debug efficiently and clearly articulate gating issues to engineering leads.
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Integrate the block level testbench at SOC level and verify SOC integration
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Involvement in post-silicon activities such as silicon bring-up, evaluation support, ATE pattern bring-up to take SoC into production.
Additional Qualifications & Experience:
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Digital Signal Processing concepts, and tools such as MATLAB or Octave
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Experience with HW emulation or FPGA prototyping is a plus