Senior Analog Validation Engineer

VLSI Testing - Post Silicon Validation of 22nm, 32nm, 45nm, 65nm and 90nm Analog IPs Programming Languages: LABVIEW, C, C , Assembly Candidate should be able to setup LabVIEW based automation for Post Silicon Validation Signal Integrity Analysis using Agilent-ADS and/ or Cadence - Allegro PCB designer Candidate should have defined, developed and executed Test Plans for Analog Electrical Characterization of advanced CMOS I/O s, Compensation blocks, DDR, BIDIRS, LVDS, PLL, Power Management Block, LDO, ADC, etc. Perform Analog electrical characterization, Signal measurements with the ATE Familiarity with High BW Oscilloscope, Pattern & Pulse Generator, Time Domain Reflectometry, Eye Analysis Education BE/ BTech (Electronics/ Electrical/ Electronics & Comm) or MSc (VLSI/ Electronics/ Electrical/ Electronics & Comm) or MS / MTech would be preferred