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Lead/Manager Design Verification Engineer

EXIMIETAS DESIGN PRIVATE LIMITED
Posted on
EXIMIETAS DESIGN PRIVATE LIMITED logo

Experience
Up to 3 yrs
Job Location
Pune, India
Vacancy
1
Designation
Lead Verification Engineer
Job Type
ONSITE

Job Description

Job Summary
Eximietas Design LLC, has openings for Lead/ManagerDesign VerificationEngineer
Role:
Role: Lead/ManagerDesign VerificationEngineer
Exp: 10+ Years
Location: Bangalore / Ahmedabad / Pune / Chennai
Minimum Qualifications
  • 10+ years ofDesign verificationexperience.
  • Strong understanding of design concepts and ASIC flow
  • Prior work experience on IP, Subsystem and Socverification.
  • Strong SV/UVM coding skills.
  • Strong understanding of RAL
  • Hands-on experience on third party VIP Integration.
  • Strong solving , analytical and debugging skills.
  • Strong understanding of AMBA protocols like generic AXI, APB, AHB
  • Hands onverificationexperience in Low speed peripherals like, I2C, SPI, QSPI, DMA, Interrupt controller, GPIO, UART
  • Hands onverificationexperience in any of the high-speed protocol like PCIE, CXL, Ethernet or USB
  • Hands on experience in any of the memory protocols like DDR, LPDDR or HBM
  • Hand on experience withverificationtools such as VCS, Xcelium, Waveform analyzer and third-party VIP integration.
  • Hands on experience with revision control flow like Git, SVN, Perforce
  • Hands on experience withGLS and Power aware simulation (UPF)
  • Experience in a team lead role, including guiding and mentoring team members, and ensuring effective collaboration and communication within the team. As a Seniorverificationengineer candidate will be responsible to work at IP, Subsystem or SoCv
    verification related tasks.
Responsibilities
  • Develop testbench components (Driver, Monitor, Scoreboard) from scratch or enhance an existing testbench for a given IP, Subsystem, or SOC.
  • Understand design specifications and implementation to define theverificationstrategy.
  • Create testbench micro-architecture, test plan, and coverage plan documents.
  • Define theverificationscope, develop test plans and tests, and establish theverificationinfrastructure to ensure design correctness.
  • Implement SystemVerilog assertions and functional coverage.
  • Analyze code coverage and address missing scenarios to meet coverage goals.
  • Work with otherverificationteam members to develop, execute, and analyzeverificationtest cases and sequences, providing relevant solutions to issues.
  • Collaborate with architects, designers, and pre- and post-siliconverificationteams to meet deadlines.
  • Coordinate with customer leads, ensuring all deliverables and timelines are met.
  • Serve as the projects point of contact, responsible forverificationsignoff.

Location - Bangalore ,Ahmedabad ,Pune ,Chennai