Hiring FPGA Design Engineers EXP - 6 + (Video Domain/Digital IP)

Mirafra Technologies is Hiring FPGA Engineer

Location: Hyderabad
Experience: 6 to 14 Years

Key Responsibilities:

• Design Register Transfer Level (RTL) IPs for video connectivity subsystems
  
• Participate in architecture, micro-architecture, documentation, and implementation
  
• Perform RTL coding for design blocks
  
• Work on front-end design methodologies including resource optimization, CDC and RDC
  
• Collaborate with cross-functional teams across different time zones
  

Required Skills:

• Experience working on Video domain IPs / Digital IPs
  
• Experience with protocols such as MIPI CSI, MIPI DSI, DisplayPort, HDMI, or SDI
  
• Hands-on experience with AMD/Xilinx FPGA devices and Vivado toolchain
  
• Strong experience in Verilog / SystemVerilog RTL coding for FPGA designs
  
• Experience with Lint, CDC, synthesis flow, STA and formal verification
  
• Knowledge of TCL / Perl / Python is an added advantage
  
• Understanding of SERDES architecture is a plus
  

Education:
Bachelors / Master’s Degree in Electronics / Electrical Engineering

Interested candidates can share their resumes to swarnamanjari@mirafra.com