Job Description
The successful candidate will own the DFX design, develop and implement cutting edge DFX features including SSN, EDT, ATPG etc. Work closely with the DFX Architecture and Design teams and SoC teams to align on the DFX requirements and successfully implement and verify the DFX features, find creative ways to accelerate the existing process.
PREFERRED EXPERIENCE:
Experience and understanding of ASIC DFX, SSN Architecture, EDT Architecture, ATPG experience in tile and SoC (die and package) level experience. Expertise in writing custom ICL and PDL.
Applicant should be familiar with scan hardware compressions, failure mechanisms, and debug processes.
IJTAG/IEEE 1687: Utilizing IJTAG infrastructure to configure SSN, create instrument connectivity language (ICL) models, and develop Procedural Description Language (PDL) commands to manage test instruments.
Familiar in ICL Extraction PDL Retargeting, from RTL/Gate Netlist to describe instrumentation and retargeting PDL commands from the IP level to the top level. EDT, SSN and SSH architecture understanding, IJTAG,EDT, TestKompress, simulation and verification flow and experience of working in DFX architecture of complex SOC patterns retargeting. Spyglass experience with RTL quality check tools such as Spyglass, Lint is required.
DFX/DV - Design for Testability/Verification: Verifying SSN and Scan architectures using gate-level simulations, SCAN architecture, TAP/JTAG related DV feature, and validating patterns. Integrating test bench with SV based test bench.
Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem. Experience in End-to-End DFX flow development/creation. Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation.
Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, EDT. Scan/ATPG patterns test flows development, debug, test, and characterization. Excellent hands-on debug skills and scripting skills are critical.
Strong communication skills and the ability to collaborate effectively within a global team environment are essential. Strong problem-solving skills.
Good to have experience:
- Hands on verification experience with C/C++/SystemVerilog/UVM testbench development.
ACADEMIC CREDENTIALS:
- Master's degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering
LOCATION: Bangalore, India
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