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STA Lead

Proxelera
Posted on

Experience
10 - 15 yrs
Job Location
Chennai, India
Vacancy
1
Designation
Lead Software Engineer
Job Type
ONSITE

Job Description

Job Title: STA Lead - 10-15Yrs
Work Location: Chennai or Bangalore(The role requires an initial 6-week work period in Chennai, followed by work at the client location in Bangalore for interested candidates)
The Job Role:
We are looking for a highly experienced STA Engineer to lead and drive full-chip and block-level timing closure for advanced nodes. The ideal candidate will have deep expertise in static timing analysis, constraint development, signoff methodologies, and cross-functional collaboration with PD, synthesis, and design teams.
Key Responsibilities:
  • Own full-chip and block-level STA from early design through signoff
  • Develop, validate, and maintain SDC constraints (clocks, I/O, exceptions, CDC-related constraints)
  • Perform timing closure across multiple modes, corners, and PVT conditions
  • Analyze and close setup, hold, recovery, removal, and min-pulse violations
  • Drive ECOs in collaboration with PD and synthesis teams
  • Lead timing signoff using industry-standard tools
  • Review and sign off timing for IP integration and SoC-level designs
  • Debug complex timing issues involving clocks, CDC, async paths, and IP interactions
  • Define and improve STA methodologies, flows, and best practices
  • Mentor junior STA engineers and act as a technical point of contact
  • Work closely with PD, RTL, DFT, Low Power, and Verification teams
Required Skills & Experience:
  • 10 15 years of hands-on experience in Static Timing Analysis
  • Strong expertise in PrimeTime / PrimeTime-SI (or equivalent STA tools)
  • Deep understanding of advanced process nodes (e.g., 7nm, 5nm, 3nm preferred)
  • Excellent knowledge of:
    • Clock tree architectures and clocking schemes
    • Multi-clock and multi-voltage designs
    • OCV, AOCV, POCV, LVF timing methodologies
    • SI effects: crosstalk, noise, and derates
  • Strong scripting skills in Tcl, Perl, or Python
  • Experience with low-power designs (UPF/CPF)
  • Proven ability to handle complex SoC timing closure
Education:
  • Bachelor s or Master s degree in Electrical / Electronics / Computer Engineering or related field

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