STA Engineer

Job Title: STA Engineer - 3-6 Yrs

Location: Hyderabad

No. Of positions: 1

Experience required: 3-6 Years

• We are looking for profiles with strong understanding of STA concepts and Timing constraints with 3-6 years of experience

• Must have solid understanding of timing constraints and their verification at SoC and block level along with good understanding of STA concepts to debug timing constraint issues.
• This role will provide SoC and block level timing constraints development exposure.
• Responsibilities will include promotion of multiple IP timing constraints to SoC level and integrating them into SoC timing constraints.

• Understanding of STA concepts and Timing constraints as well as VLSI design flow;
• Familiarity with Verilog, timing (.lib), LEF, GDS; Familiarity with physical design verification, e.g. DRC and LVS; Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language. 3-6 years of experience

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