Senior Staff ASIC Verification Engineer

Role: As a Senior Staff ASIC Verification Engineer, you will lead the planning, development, and execution of verification strategies for complex ASIC designs. You will work closely with ASIC design teams to validate that the ASICs meet functional and performance requirements. This role involves overseeing verification activities, managing verification teams, and ensuring comprehensive coverage of test scenarios. The position demands advanced technical skills, a strong understanding of verification methodologies, and leadership experience.

Qualifications

• Bachelors or Masters degree in Electronics and Communications Engineering, Electrical and Electronics Engineering, or a related field.
• 10+ experience in ASIC verification. Proven track record in leading verification projects and managing verification teams.
• Proficiency in hardware description languages (SystemVerilog, VHDL).
• Experience with ASIC verification tools and environments (e.g., Cadence, Synopsys, Mentor Graphics).
• Deep understanding of UVM (Universal Verification Methodology) or other advanced verification frameworks.
• Knowledge of digital logic design and ASIC design principles.
• Strong leadership and team management skills.
• Excellent problem-solving and analytical abilities.
• Effective communication and interpersonal skills.
• Ability to work collaboratively with cross-functional teams and stakeholders
• Experience in project management and coordination of complex verification projects.
• Ability to manage timelines, resources, and project scope effectively.

Location: Hyderabad