Senior Functional Validation Engineer

Development & bring-up of Pre Silicon Validation platforms like Palladium or FPGA for the IP/ SOC Development & bring-up of Silicon Validation platforms like Validation Board & Silicon (EVB, ATE etc.) for new IP/ SOC design Development of validation plans, Coding and Debug of scenarios on Pre and Post Silicon platform Creating and performing system use scenarios Methodology development for quality and execution efficiency Ability to work well as part of a team both locally, and also with remote or multi-site teams Specific Knowledge/ Skills: 3-7 years of experience in validating IPs/ SOC of multimillion Gate and complex design with multiple clocks and power domains Test plan and test code development to address functional and integration requirements of the IP/ SOC. Experience and working knowledge of verilog and C/ C is must. Expertise of using compiler & debugging tools like CodeWarrior, GHS, Lauterbach Good Software Architecture knowledge Working knowledge of Palladium & FPGA platform Multilayer Board design, testing, integration capabilities Expertise of High Speed Industry protocol Validation like USB, SATA, ETHERNET, DDR Knowledge of Multimedia applications, embedded programming Expertise in using test equipment s used in validation (Logic Analyzers, High Speed CRO, Protocol Analyzers, Spectrum Analyzer, and Network Analyzer) Experience in working on ColdFire, PowerPC, ARM core architectures would be an advantage. Applicants must be willing to work in Noida Industry Type: Semiconductor, Electronics, System Design, Applications, Embedded hardware and Software Functional Area: Silicon Validation, Reference Design, Applications Design Keywords: ASIC, SOC, VALIDATION, SILICON, VERILOG, EMBEDDED, HARDWARE DESIGN, PALLADIUM, FPGA Education BE/ B-Tech (Electronics/ Electrical/ Electronics & Comm) or MSc (VLSI/ Electronics/ Electrical/ Electronics & Comm) or MS / MTech would be preferred