Senior ASIC Design Engineer

Job Summary

We are seeking an experienced ASIC Design Automation Engineer to join our world-class team, building leading-edge chips for the Coherent Optics market. The ideal candidate will possess a Bachelor's or Master's degree in Electrical or Computer Engineering, coupled with a minimum of 5 years of relevant experience, including at least 2 years in RTL design. Key qualifications include strong expertise in Synthesis, STA, and constraints development, alongside proficiency in Shell, Perl, TCL, and other scripting languages. Knowledge of Synopsys Electronic Design Automation (EDA) tools, Verilog/System Verilog, and LSF is highly valued. This role involves automating CAD flows, developing new methodologies, and collaborating with design teams to enhance efficiency and quality in ASIC development.

Job Description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise.

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we've united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

Work as part of a world class ASIC design team, building leading edge chips for the Coherent Optics market.

Key Responsibilities

As a member of the ASIC design team, you will play the role to automate CAD flows for ASIC design. Your contributions will include:

• Develops and maintains key common RTL IP modules used at every product generation.
• Interacts with RTL designers to understand the flow of work, develops the architecture to automate the flow and then implements the automation to eliminate pain points and errors to de-risk projects.
• Develop Synthesis flows and run synthesis alongside with other designers and provide feedback to designers to improve timing and power.
• Develops scripts to automate using Python, Perl or other scripting languages.
• Works as part of a methodology team to develop new CAD/methodologies or flows which improve quality of design, reduce design time and provide consistent and reliable results across users and sites and streamline the process of ASIC development.
• Identifies input variables, categorizing them as fixed or customizable or user controllable options allowing users to have simplified interaction with the tool flow.
• Identifies scope for improvement in existing flows and implement those improvements.
• Work with experts and users across sites to identify new methodologies for development and adoption.
• Works with EDA tool vendors to identify options available across tools which reduce debug and development effort. Takes the options and make them available in a simplified way to design engineers.
• Works with EDA tool vendors to evaluate new tools and new features.
• Develops flows, take it through a proof-of-concept on a project and release the flow for production use across teams and sites.
• Makes presentations to teams to ramp users about improvements or new flow development.
• Works on EDA tool installation and support, compute platform support, LSF job submittal support, infrastructure related support for worldwide ASIC design community.
• Works closely with IT and debug and implement solutions.
• Continuously monitor/improve CAD infrastructure efficiency and CAD automation.

The job is a high visibility job and has the potential to improve and impact the work of multiple engineers across geographies.

Requirements

• Hold a Bachelor or master's degree in electrical or computer engineering.
• Have a minimum 5 years of experience with relevant experience.
• Have a minimum 2 years of RTL design experience.
• Strong experience in Synthesis, STA and constraints development.
• Strong working experience of Shell, Perl, TCL and other programming/scripting language.
• Strong problem-solving skills.
• Good verbal/written communication skills and teamwork.
• Knowledge of Synopsys Electronic Design Automation (EDA) tools an asset.
• Knowledge of Verilog or System Verilog.
• Knowledge of LSF.
• Knowledge of machine learning and/or neural networks may be an asset.