RTL Design Engineer- Lead

Location: Bangalore / Noida
Experience: 10-15 Years
Notice Period: Open to all notice periods

Job Description:
Strong experience in RTL Design / ASIC / SoC Design
Hands-on expertise in Verilog / SystemVerilog / VHDL
Experience in micro-architecture development, RTL coding, and design integration
Strong understanding of SoC architecture and industry-standard protocols such as AXI, AHB, APB, PCIe, USB, etc.
Experience in timing closure, synthesis, and low-power design concepts
Ability to lead design teams and drive end-to-end project execution
Strong debugging and problem-solving skills
Excellent stakeholder management and communication skills