Experience
2 - 6 yrs
Salary (CTC)
₹9.6L - ₹13.8L
Job Location
Noida, India
Vacancy
1
Designation
Physical Verification Engineer
Job Type
Not specified
Job Description
Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey
Join us for unparalleled growth and development, Responsibilities:-
Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules
Collaborate with layout designers to resolve DRC issues, Layout vs
Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies, Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended, Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process
Address lithography and process variation concerns, Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication, Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process, Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress, Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations, Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues, Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics, Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process, Documentation: Maintain detailed documentation of verification processes, methodologies, and results, Qualifications:BTECH/MTECH
Experience:The Engineers with 5+ years of Experience
Location:Bangalore/ Noida
Join us for unparalleled growth and development, Responsibilities:-
Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules
Collaborate with layout designers to resolve DRC issues, Layout vs
Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies, Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended, Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process
Address lithography and process variation concerns, Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication, Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process, Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress, Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations, Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues, Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics, Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process, Documentation: Maintain detailed documentation of verification processes, methodologies, and results, Qualifications:BTECH/MTECH
Experience:The Engineers with 5+ years of Experience
Location:Bangalore/ Noida