Job Description

1. Proficient in Verilog coding and RTL design, data path designs,

2. Knowledge of RTL checks ex- LINT, SDC, CDC

3. Familiar with synthesis flow and timing constraints

4. Experience in writing Verilog testbench and running simulations.

5. Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

Lead Design Engineer

Job Description

No Referrers Available