Develop analog circuits for high-speed DDR and other IO applications in advanced FinFET nodes
Work with IO lead to understand the design requirements and translate them into circuit architectures and implement and simulate them.
Circuit design, simulation and optimization of various IO blocks such as clocking (PI, DLL, PLL), CTLE, VGA, Tx, Rx, DFE, etc.
Develop the calibration and training algorithms of various sub-blocks in the IO s to meet high-speed performance.
Work closely with layout engineers on floorplan and placement of their designs. Create efficient power delivery and signal routing topology to reduce congestion.
Create Verilog and functional models for their designs. Perform AMS simulation to verify functionality of designs.
Evaluate new design architectures and circuit implementation techniques to continuously improve the current and future IO design.
Support IO Mixed-Signal IP through post-tapeout phase, including lab testing, customer bring-up and debug

Requirements/Qualifications:

Experience Required

8+ years of experience in design and verification of mixed signal blocks in complex SoC.
Experience with Virtuoso schematic capture tool.

Requirements

Minimum of 6years of successful prior IO development and verification efforts.
Competency in HSPICE, co-sim, and testbench generation and simulation.
Knowledge about high-speed design techniques (DDRx, PCI-e, USB) and calibrations from an architectural and circuit design standpoint.
Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel.
Power analysis.
Good analytical, oral and written communication skills
Able to write clean, readable presentations.
Self-motivated, proactive team player.
Ability to work to schedule requirements.

IO Mixed Signal Design Engineer

Job Description