Job Description
FPGA / ASIC Design & Integration Engineer
Experience Required
5 to 12 Years
Job Location
Bangalore / Bengaluru (Work from Office)
Salary / CTC
As per industry standards / Negotiable based on experience
Industry / Functional Area
Engineering - Hardware / VLSI / ASIC / Chip Design
Job Description (Paste in the Main Body Field)
Welcome to a World of Innovation!
ACL Digital, a proud subsidiary of the Alten Group, invites you to shape the future of silicon technology with a global leader in engineering and digital product development. Come build next-generation hardware architectures with us at our Bangalore design center!
We are seeking a highly skilled and dynamic FPGA/ASIC Design Engineer to join our growing silicon engineering team. In this role, you will be responsible for the micro-architecture, RTL coding, block-level synthesis, and top-level integration of high-performance semiconductor solutions. You will work closely with cross-functional teams to bring up complex subsystems in the lab, focusing heavily on high-speed protocols like PCIe and Ethernet.
Key Responsibilities:
- RTL Design & Architecture: Design and implement block-level RTL logic using Verilog, VHDL, or SystemVerilog. Participate actively in defining micro-architecture and detailed design specifications.
- Top-Level RTL Integration: Stitch together complex IP blocks, subsystems, and memory controllers using standard bus fabrics (AXI, AHB, APB). Manage clock domain crossings (CDC), reset domain crossings (RDC), and top-level pin/pad multiplexing.
- Synthesis & Timing Closure: Perform logic synthesis and structural quality checks (Lint, CDC analysis). Drive timing closure and generate bit-files for targeted FPGA architectures.
- Protocol Implementation: Implement, integrate, and debug high-speed and standard interfaces, with a specific focus on PCIe and Ethernet (MAC/PHY) protocols, alongside standard peripherals (SPI, I2C, UART).
- Verification & Validation: Collaborate with verification teams to run functional simulations. Assist in subsystem-level lab bring-up, hardware debugging, and post-silicon validation using JTAG, logic analyzers, and oscilloscopes.
Required Skills and Experience:
- Languages: High proficiency in Verilog and/or VHDL; working knowledge of SystemVerilog.
- FPGA Tools & Platforms: Hands-on experience with FPGA vendor toolchains like Xilinx Vivado or Altera/Intel Quartus.
- Core Protocols (Must-Have): Direct experience working with PCIe and Ethernet protocols, as well as AMBA AXI interconnect architectures.
- Peripherals: Practical knowledge of low-speed serial interfaces (I2C, SPI, UART).
- Quality & Sign-off: Experience with structural design checks like Clock Domain Crossing (CDC) analysis and Linting.
- Lab Debugging: Strong hands-on experience in post-silicon system validation, chip bring-up, and hardware troubleshooting.
Added Advantages:
- Familiarity with verification flows like UVM.
- Basic scripting (TCL, Perl, Python) for automation.
- Experience with ASIC synthesis tools (e.g., Synopsys Design Compiler).
Candidate Preferences:
- Notice Period: Immediate to 30 Days preferred.
- Location: Candidates must be currently residing in or willing to relocate immediately to Bangalore.