Digital Verification Engineer

Job Description Summary

We are developing state-of-the-art SoCs from architecture to final product involving automotive centric design methodologies and flows tailored for functional safety. We have a presence across multiple geographies and are currently in search of a Principal level IP/SoC Design Verification Engineer.

RESPONSIBILITIES

• Develop testbenches using System Verilog and UVM for functional and power aware RTL

• Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage.

• Develop test plan, UVM based test sequences, layered sequences, virtual sequencers

• Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation.

• Develop C testcases for HW-FW simulation and FPGA prototyping

• Provide regression setup, debug of RTL and gate level netlist

• Review industry standard spec and augment test plan to improve quality of verification

• Participate in post silicon bring up, validation and compliance testing and debug

• Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product

MINIMUM QUALIFICATIONS

• Proven track record of verification, taking several chips from specification to tape out

• Proven expertise with UVM and/or System Verilog based verification

• Excellent understanding of ASIC verification methodologies and proven experience of verification

• Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira.

• Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus.

• Strong written and verbal communication skills and ability to work independently.

• Bachelors in Electrical Engineering or equivalent and 5+ years of experience

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