ASIC DV Engineer, Simulation Acceleration and Verification

We are looking for a skilled ASIC DV Engineer with expertise in Simulation Acceleration and Hybrid Verification to join our team at Meta. The ideal candidate will have a strong background in verification methodologies and tools, with experience working on complex digital designs.

Roles and Responsibility

• Design and develop verification environments for complex digital circuits using SystemVerilog and other relevant tools.
• Collaborate with cross-functional teams to identify and prioritize verification requirements.
• Develop and implement simulation-based verification strategies to ensure design quality and reliability.
• Utilize simulation acceleration techniques to improve verification efficiency and reduce turnaround times.
• Analyze and debug verification results to identify defects and provide recommendations for improvement.
• Participate in the development of hybrid verification methodologies and standards.

Job Requirements

• Strong understanding of SystemVerilog, UVM, and other relevant verification methodologies and tools.
• Experience with simulation acceleration techniques and hybrid verification methodologies.
• Familiarity with industry-standard verification flows and methodologies.
• Strong analytical and problem-solving skills, with attention to detail and ability to work independently.
• Excellent communication and collaboration skills, with the ability to work effectively with cross-functional teams.
• Bachelor's degree in Computer Science, Electrical Engineering, or related field.

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.