ASIC / IP / SOC Verification Engineer

QUALIFICATION: 4-12+ YEARS EXPERIENCE
B. Tech/M. Tech in Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience

• Hiring for Senior Engineer, Technical Lead, and Architect levels

• Dedicated/hands-on ASIC/IP/SOC DV experience

• Experience working on block level UVM test benches - writing drivers, scoreboards, sequences, constraints, and functional coverage models

• Strong interest in understanding the architectural and micro-architectural details of a design

• Strong interest in debugging complex issues

• Drive and adopt new verification methodologies to improve effectiveness and efficiency

• Experience working on the memory subsystem is a plus

• Build UVM test benches and own the verification of an IP from start to finish. Create coverage driven verification plans from specifications. Execute, review and refine to achieve coverage targets

• Set up regressions and triage failures. Debug and drive any design and verification bugs found, to closure

• Work with the team to improve DV methodology and infrastructure

• Proven experience in scripting languages such as Python / Perl / TCL